1 of 9 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? directly replaces 2k x 8 volatile static ram or eeprom ? unlimited write cycles ? low - power cmos ? jedec standard 24 -pi n dip package ? read and write access times of 100 ns ? full 10% operating range ? optional industrial temperature range of - 40c to +85c, designated ind pin assignment 24- pin en capsulated package 720- mil extended pin description a0 -a10 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enable oe - output enable v cc - power (+5v) gnd - ground description the ds1220y 16k nonvolatile sram is a 16,384 - bit, fully static, nonvolatile ram organized as 2048 words by 8 bits. each nv sram has a self - contained lithium energy source and control circuitry that constantly monitor v cc for an o ut - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is un conditionally enabled to prevent data corruption. the nv sram can be used in place of existing 2k x 8 sram s directly c onforming to the popular bytewide 24 - pin dip standard. the ds1220y also matches the pinout of the 2716 eprom or the 2816 eeprom, allowing direct substitution while enhancing perform ance. there is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 14 vcc we 1 2 3 4 5 6 7 8 9 10 11 12 13 24 15 23 22 21 20 19 18 17 16 a7 a5 a3 a2 a1 a0 dq0 dq1 gnd dq2 a6 a4 a8 a9 oe a10 ce dq7 dq6 dq5 dq3 dq4 ds1220y 16k nonvolatile sram not recommended for new designs www.maxim - ic.com 19 - 5579; rev 10/10 downloaded from: http:///
not recommended for new designs ds1220y 2 of 9 read mode the ds1220y executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 11 a ddress inputs (a0 - a10) defines which of the 2048 bytes of data is to be accessed. valid data wi ll be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe access times are also satisfied. if ce and oe access times are not satisfied, then data access must be measured from the later - occurring signal and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1220y executes a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are en abled ( ce and oe active) then we will disable the o utputs in t odw from its falling edge. data retention mode the ds1220y provides full - functional capability for v cc greater than 4.5 volts and write protects at 4.25 nominal. data is maintained in the absence of v cc without any additional support circuitry. the ds1220y constantly monitors v cc . should the supply voltage decay, the nv sram automatically write protects itself, all inputs become dont care, and all outputs be come high - impedance. as v cc falls below approximately 3.0 volts, a power switching cir cuit connects the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operati on can resum e after v cc exceeds 4.5 volts. downloaded from: http:///
not recommended for new designs ds1220y 3 of 9 absolute maximum ratings voltage range on any pin relative to ground - 0.3v to + 6. 0v operating temperature range commercial: 0 c to +70 c industrial: -40 c to +85 c storage temperature -40 c to +85 c lead temperature (soldering, 10 s) +260c note: edip is wave or hand soldered only . this is a stress rating only and functional operation of the device at these or any other condit ions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended pe riods of time may affect reliabil ity. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes power s upply voltage v cc 4.5 5.0 5.5 v input logic 1 v ih 2.2 v cc v input logic 0 v il 0.0 +0.8 v dc electrical characteristics (t a : see note 10; v cc = 5v 10%) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 3.0 7.0 ma standby current ce =v cc - 0.5v i ccs2 2.0 4.0 ma operating current t cyc = 200ns (commercial) i cco1 75 ma operating current t cyc =200ns (industrial) i cco1 85 ma write protection voltage v tp 4.25 v capacitance (t a = + 25c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 12 pf downloaded from: http:///
not recommended for new designs ds1220y 4 of 9 ac electrical characteristics (t a : see note 10; v cc = 5.0v 10%) parameter sym ds1220y-100 units note s min max read cycle time t rc 100 ns access time t acc 100 ns oe to output valid t oe 50 ns ce to output valid t co 100 ns oe or ce to output active t coe 5 ns 5 output high - z from des e lection t od 35 ns 5 output h old from address change t oh 5 ns write cycle time t wc 100 ns write pulse width t wp 75 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 0 10 ns ns 12 13 output high - z from we t odw 35 ns 5 output active from we t oew 5 ns 5 data setup time t ds 40 ns 4 data hold time t dh1 t dh2 0 10 ns ns 12 13 downloaded from: http:///
not recommended for new designs ds1220y 5 of 9 read cycle see note 1 write cycle 1 see notes 2, 3, 4, 6, 7, 8 and 12 write cycle 2 see notes 2, 3, 4, 6, 7, 8 and 13 downloaded from: http:///
not recommended for new designs ds1220y 6 of 9 power - down/power - up condition see note 11 power - down/power - up timing parameter symbol min max units notes ce at v ih before power - down t pd 0 s 11 v cc slew from v tp to 0v t f 100 s v cc slew from 0v to v tp t r 0 s ce at v ih after power - up t rec 2 ms (t a = +25 c) parameter symbol min max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during a write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. downloaded from: http:///
not recommended for new designs ds1220y 7 of 9 6. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during thi s period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output b uffers remain in a high impedance state during this period. 9. each ds1220y is marked with a 4 - digit date code aabb. aa designates the year of manufacture. bb designates the week of manufacture. the expected t dr is defined as starting at the date of manufacture. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, this range is 0c to 70c. for industrial produc ts (ind), this range is - 40c to +85c. 11. in a power - down condition the voltage on any pin may not exceed the voltage of v cc . 12. t wr1 , t dh1 are measured from we going high. 13. t wr2 , t dh2 are measured from ce going high. 14. ds1220y modules are recognized by underwriters laboratories (ul ? ) under file e99151 (r). dc test conditions outputs open. all voltages are referenced to ground. ac test conditions output load: 100pf + 1ttl gate input pulse levels: 0 -3.0v timing measurement reference levels input:1.5v output: 1.5v input pulse rise and fall times : 5ns ordering informatio n part temp range supply tolerance pin - package ds1220y-100+ 0c to +70c 5v 10% 24 / 720 edip DS1220Y-100IND+ - 40c to +85c 5v 10% 24 / 720 edip + denotes a lead (pb) - free/rohs - compliant package. downloaded from: http:///
not recommended for new designs ds1220y 8 of 9 pkg 24 -pin dim min max a in. mm 1.320 33.53 1.340 34.04 b in. mm 0.695 17.65 0.720 18.29 c in. mm 0.390 9.91 0.415 10.54 d in. mm 0.100 2.54 0.130 3.30 e in. mm 0.017 0.43 0.030 0.76 f in. mm 0.120 3.05 0.160 4.06 g in. mm 0.090 2.29 0.110 2.79 h in mm 0.590 14.99 0.630 16.00 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.38 0.021 0.53 pack age information for the latest package outline information and land patterns , go to www.maxim -ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regard less of rohs status. package type package code outline no. land pattern no. 24 dip mdt24+3 ? 21-0245 downloaded from: http:///
not recommended for new designs ds1220y maxim r cannot assume responsibility for use of any circuitry other than circuitr y entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notic e at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 20 10 maxim integrated products maxim and the dallas logos are regis tered t rademark s of maxim integrated products, inc . 9 of 9 revision history revision date description pages changed 121907 added the package information table; removed the dip module package drawing and dimension table 7 072808 added the dip module package drawing and dimension table 8 10/10 updated the soldering information in the absolute maximum ratings section, removed the unused ac timing specs in the ac electrical characteristics table, updated the ordering informatio n table, updated the package information table 1, 3, 4, 7, 8 downloaded from: http:///
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